Circuit arrangement with combinatorial blocks arranged between registers

ABSTRACT

In the circuit arrangement, combinatorial blocks are arranged between an input register (RG 1 ) and an output register (RG 2 ). The output of the input register (before the combinatorial blocks (KBL)) is connected to an analysis unit (ANA) that analyzes the value (EW) of the output of the input register (RG 1 ) and send an enable signal (EN) to the output register (RG 2 ) (after the combinatorial blocks) when the output value (AW) of the combinatorial blocks (KBL) must be present after the value (EW) of the output of the input register (RG 1 ). The transit time required for an operation in the circuit arrangement can thus be shortened given certain value combinations.

BACKGROUND OF THE INVENTION

In the development of synchronous circuits, what are referred to ascombinatorial blocks KBL(see FIGS. 1 and 2) are always located betweenregisters (referenced input register RG1 and output register RG2 below).There are currently 3 principles of arranging combinatorial blocks andregisters in order to adhere to the physically conditioned setup andhold times:

The transit time/delay time KBL-VZ of value changes through thecombinatorial blocks KBL is shorter than the clock pulse period minusthe setup time Setup/Hold-VZ and minus the signal propagation time RG-VZthrough a register RG. This is shown in FIG. 1. A combinatorial blockKBL is switched between an input register RG1 and an output registerRG2. The registers RG1 and RG2 are driven by a clock pulse T.

The transit time of value changes through the combinatorial blocks KBLis greater by a factor N than a clock period of the clock pulse signalT. The outcome, however, is only picked up after N clock impulse signalsat the exit of the output register RG2 behind the combinatorial blocksKBL.

The transit time of value changes through the combinatorial blocks KBLis greater by a factor N than a clock period of the clock pulse signalT. The outcome, however, is only stored in the output register RG2behind the combinatorial blocks KBL after N clock pulse signals. To thatend, an enable terminal EN at an output register RG2 is driven with apulse that is delayed by N clock pulse signals and generated by acontrol circuit CON (see FIG. 2).

The transit time KBL-VZ through the combinatorial circuit KBL, however,is extremely value-dependent. This means that, in some cases, the outputvalue could be clocked into the output register RG2 in the circuitarrangement (shown in FIG. 2) after M<N cycles. The processing speed ofa sequential logic system, in which the circuit arrangement (shown inFIG. 2) is embedded, could thus be increased.

German Letters Patent DE 36 06 406C2 discloses a circuit arrangementwherein combinatorial blocks are provided whose output signals areoutput to output registers which are switched behind these blocks.Further, sequential logic systems with combinatorial blocks and memoryunits are disclosed in German Patent DE 42 06 082C1 and Europeanapplication EP 04 56 399A2.

SUMMARY OF THE INVENTION

It is an object of the present invention to modify the above circuitarrangement such that the temporal behavior is ameliorated.

In general terms the present invention is a circuit arrangement withcombinatorial blocks arranged between registers. The output of the inputregister that is switched in front of the combinatorial blocks isconnected with an analysis unit that analyzes the value of the output ofthe input register. The analysis unit sends an enable signal to theoutput register behind the combinatorial blocks when the output value ofthe combinatorial blocks has to be present according to the value of theoutput of the input register.

Advantageous developments of the present invention are as follows.

A spike filter is switched between the combinatorial blocks and theoutput register.

The combinatorial block is a multiplier. The analysis unit outputs anenable signal when the more significant places of the multiplicands arezero. A logical circuit is arranged behind the multiplier that sets themore significant places of the output value of the multiplier to zero inthis case.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the present invention which are believed to be novel,are set forth with particularity in the appended claims. The invention,together with further objects and advantages, may best be understood byreference to the following description taken in conjunction with theaccompanying drawings, in the several Figures of which like referencenurtierals identify like elements, and in which:

FIG. 1 depicts a prior art circuit arrangement with combinatorialblocks;

FIG. 2 depicts another prior art circuit arrangement with combinatorialblocks;

FIG. 3 depicts a circuit arrangement for ameliorating temporal behavior;and

FIG. 4 depicts an embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Register RG refers to a clocked memory unit independently of whether itis an embodiment that only stores one bit (Flip-Flop) or can store aplurality of bits. Herein, a register does not only refer to a memoryelement that can accept an input value, but, additionally oralternatively, can also set, reset (for example JK-Flip-Flop), orpartially store (Flip-Flop/Register with Enable) a value. Furthermore, aregister can also have an additional asynchronous setting or resettinginput.

FIG. 3 shows the circuit arrangement with which the temporal behaviorcan be ameliorated. An analysis unit ANA is inserted that analyzes thevalues EW of the output of the input register RG1 to determine if avalue combination is present that allows the outcome AW to be takenearlier at the output of KBL. The analysis unit ANA also sets the enablesignal EN at the output register RG2 value-dependently, 'whereby theoutcome is clocked into the output register sooner.

Spikes might possibly occur given certain signals AW. In order to filterout such spikes, the circuit arrangement can be supplemented by the unitSpike Filter Fl that imprints a value for these signals, which can beeasily and quickly determined from the values EW.

The circuit arrangement can be designed such that all or only a part ofthe inputs are analyzed in the unit ANA, and that all or only part ofthe outputs of KBL are provided with a Spike Filter Fl.

FIG. 4 shows an embodiment of the present invention disclosed above.Therein, a multiplier MLT is shown for the multiplication of twomultiplicands MULT1 and MULT 2, each which has two four Byte inputs andtwo two Byte outputs. The more significant inputs (one Byte each) arereferenced with MSB; the less significant inputs (one Byte each) arereferenced with LSB; accordingly, the more significant inputs (two Byteseach) are referenced with A-MSB and the less significant outputs (twoBytes each) with A-LSB. The result of the multiplication is called ERG.Let the multiplier MLT be solely combinatorially constructed.

If only zeros pend at one or both of the more significant inputs of themultiplier MLT, that is, only two small numbers are multiplied, then onecan easily and quickly predict (in the circuit arrangement by ORoperation over all inputs) that only zeros also appear at one or bothmore significant outputs A-MSB of the multiplier. These appear on theseoutputs via an AND operation. Furthermore, it is known that the lesssignificant places A-LSB of the multiplier will reach their valuesearlier than those of the complete multiplier. This is indicated in thatthe line LTS at the output of the OR circuit is set to the value 0. Thispends at the unit ANA (not shown in FIG. 4) which controls the storingof the results ERG of the multiplication in the output register RG2. Theenable signal EN for this register can thus be activated sooner, and theresult ERG can be entered into the output register RG2 faster and thusbe further-processed more quickly.

The invention is not limited to the particular details of the apparatusdepicted and other modifications and applications are contemplated.Certain other changes may be made in the above described apparatuswithout departing from the true'spirit and scope of the invention hereininvolved. It is intended, therefore, that the subject matter in theabove depiction shall be interpreted as illustrative and not in alimiting sense.

What is claimed is:
 1. A circuit arrangement with at least onecombinatorial block arranged between registers, comprising: an inputregister of said registers having an output connected to an input of thecombinatorial block, and an output register of said registers having aninput connected to an output of the combinatorial block; and an analysisunit the output of the input register also connected to the analysisunit that analyzes a value of the output of the input register and thatsends an enable signal to the output register when an output value ofthe combinatorial block is present according to the value of the outputof the input register.
 2. The circuit arrangement according to claim 1,wherein a spike filter is connected between the output of thecombinatorial block and the input of the output register.
 3. The circuitarrangement according to claim 1, wherein the combinatorial block is amultiplier that receives multiplicands, wherein the analysis unitoutputs an enable signal when more significant places of themultiplicands are zero, and wherein, a logical circuit is connected tothe multiplier that sets more significant places of an output value ofthe multiplier to zero.
 4. A circuit arrangement with at least onecombinatorial block arranged between registers, comprising: an inputregister of said registers having an output connected to an input of thecombinatorial block, and an output register of said registers having aninput connected to an output of the combinatorial block; an analysisunit, the output of the input register also connected to the analysisunit that analyzes a value of the output of the input register and thatsends an enable signal to the output register when an output value ofthe combinatorial block is present according to the value of the outputof the input register; and a spike filter connected between the outputof the combinatorial block and the input of the output register, thespike filter being connected to and controlled by the analysis unit. 5.A circuit arrangement with at least one combinatorial block arrangedbetween registers, comprising: an input register of said registershaving an output connected to an input of the combinatorial block, andoutput register of said registers having an input connected to an outputof the combinatorial block; an analysis unit, the output of the inputregister also connected to the analysis unit that analyzes a value ofthe output of the input register and that sends an enable signal to theoutput register when am output value of the combinatorial block ispresent according to the value of the output of the input register; thecombinatorial block being a multiplier that receives multiplicands,wherein the analysis unit outputs an enable signal when more significantplaces of the multiplicands are zero; a logical circuit connected to themultiplier that sets more significant place of an output value of themultiplier to zero when the more significant places of the multiplicandsare zero.
 6. The circuit arrangement according to claim 5, wherein aspike filter is connected between the output of the combinatorial blockand the input of the output register.
 7. The circuit arrangementaccording to claim 6, wherein the spike filter is connected to andcontrolled by the analysis unit.